1. Field of the Invention
This invention relates to a Josephson memory circuit which stores binary information as the presence or absence of at least one flux quantum captured in its superconducting memory loop and more particularly to such a Josephson memory circuit which enables the equivalent of nondestructive read-out to be conducted simply and reliably.
2. Prior Art Statement
FIG. 3 shows an example of a typical conventional Josephson memory circuit of the type which represents the binary values "1" and "0" in terms of whether or not at least one flux quantum is captured in its superconducting loop, namely, in terms of whether or not a persisting loop current is flowing therein. This circuit consists basically of a plurality of Josephson cells 10.sub.-1 -10.sub.-n constituted as ac-superconducting quantum interference devices (ac-SQUIDs) and connected in series as a column of memory cells by a single circuit current line 12. Generally, a plurality of such memory cell columns are disposed in the row direction so as to form a memory space constituted as an ordinary X-Y matrix. For indicating that there are a plurality of current lines 12 interconnecting the respective memory cell columns, the notation in the same figure is followed by (12.sub.-i), where i=1, 2, 3 . . .
Each of the Josephson memory cells 10 has a superconducting memory loop 11 for capturing a prescribed number of flux quanta. The superconducting memory loop 11 has therein at least one Josephson switch J.sub.S whose critical current value is controlled by means of an external control current I.sub.X applied to a magnetically coupled control signal line 13 and a pair of current injection terminals P.sub.1, P.sub.2 for connecting the superconducting memory loop 11 in series with the circuit current line 12.
Depending on the moment-to-moment operating state of the cell, one of the current injection terminals P.sub.1, P.sub.2 is n the current inflow side and the other is on the current outflow side. From the viewpoint of either of the current injection terminals P.sub.1, P.sub.2, the superconducting memory loop 11 can be seen as being constituted of left and right branches. In the illustrated example, the Josephson switch J.sub.S is included in series connection within the left branch and an inductance L.sub.C is included in series connection within the right branch. While the left branch also includes an inductance component, it is generally advantageous to establish a large difference between the inductance components of the two branches and, therefore, it is a common practice to ignore the inductance component of the branch including the Josephson switch J.sub.S when representing a memory circuit of this type schematically. The drawing thus deliberately shows only the inductance L.sub.C (which is of not less than a prescribed value) as being concentrated at one location.
Where an X-Y matrix is to be constituted in the manner described above to serve as a Josephson memory circuit, it is possible to have the control currents I.sub.X for controlling the Josephson switches J.sub.S of the individual superconducting memory loops 11 within the memory cell column double as, for example, the X selection (row selection or word selection) currents. In the drawing, therefore, the control currents I.sub.X are assigned parenthetical row number suffixes I.sub.X-1, I.sub.X-2, . . . , I.sub.X-n and the control signal lines 13 are assigned corresponding suffixes.
In the ensuing description, however, the suffixes of symbols designating the respective circuit elements and currents will be omitted unless they are necessary for indicating a specific column or row or for distinguishing between different columns and rows.
There will now be described a typical example of the operation conducted when a binary value is to be written to a specific address (i.e. to a specific memory cell 10.sub.-ji ; where j=1, 2, . . . , n). (For the purpose of the description, binary "1" is defined to be represented by the state in which a prescribed number of flux quanta are captured in the superconducting memory loop 11, specifically by the state in which a persisting loop current I.sub.L is present.)
Say, for example, that binary "1" is to be written to Josephson memory cell 10.sub.-i. In this case, a control current I.sub.X-i of a significant value other than zero is applied as the row selection current and the circuit current I.sub.Y-i is similarly made to assume a significant value other than zero. In contrast, when binary "0" is to be written, only the control current I.sub.X-i is increased to a significant value while the circuit current I.sub.Y-i is maintained at zero (is not applied). Then after the lapse of a period of time preset for the write mode, the control current I.sub.X-i is returned to zero, whereafter the circuit current I.sub.Y-i is returned to zero (unless the operation was for writing binary "0", in which case it is already at zero). The operation for writing binary "1" causes a prescribed number of flux quanta to be captured by the superconducting memory loop 11.sub.-i of the Josephson memory cell 10.sub.-i, with the result that a persisting loop current I.sub. L is established as indicated by the broken line in FIG. 3. On the other hand, no significant current is present in the superconducting memory loop 11.sub.-i following the writing of binary "0".
Although the specific arrangement of the switching gates and other peripheral circuits conventionally employed for selectively switching the circuit current I.sub.Y and the control current I.sub.X during the binary value writing operation may vary somewhat in structure, they are by and large substantially identical in principle. In contrast, the fact that nondestructive reading of the binary values stored in the cells requires some special technique has led to the development of various methods for this purpose.
Among these, one exhibiting numerous advantages over other methods is disclosed in the applicant's Japanese Patent Public Disclosure 63(1988)-285798, according to which nondestructive reading is achieved by using the sense current which flows at the time of reading binary "1" both as sense current and also for rewriting binary "1" to the memory cell with respect to which the reading was conducted. FIG. 4 shows a specific example of a circuit for conducting nondestructive read-out according to the teaching of this earlier invention. In the illustrated circuit, one end of a memory cell column, which can be of substantially the same structure as that shown in FIG. 3, specifically one end of the circuit current line 12 interconnecting the memory cells of the column, is connected with a set gate 21, while the other end thereof is connected with a sense gate 22 via a reset gate 25. Since the sense gate 22 is generally one having a gain factor, it is frequently referred to as a sense amplifier and is so indicated in the drawing.
Under application of current I.sub.W from the power source, the voltage state of the set gate 21 switches over when its control input terminal receives a binary "1" write command current I.sub.M or, as will be explained later, receives an output current (sense current) I.sub.S from the sense amplifier 22. On the other hand, under the application of current I.sub.R from the power source, the sense amplifier 22 switches its voltage state when its control terminal receives a read current I.sub.LO (to be explained later) and, upon switching over, outputs the current I.sub.S to the load impedance R.sub.L at a prescribed gain. On the other hand, when the control currents I.sub.M, I.sub.S, I.sub.LO are not being applied, the gates 21, 22 maintain a zero voltage state even if the power source current I.sub.W or I.sub.R is applied thereto and both their inputs and outputs are dropped to ground potential (as indicated by the symbol E next to set gate 21).
In such state, therefore, one end of the circuit current line 12 is connected with ground E through the output of the set gate 21 and the superconducting path (not shown) within the set gate 21, while the other end thereof is connected with ground E through the reset gate 25 and the superconducting path (not shown) within the sense amplifier 22. The circuit board of this type of Josephson memory circuit generally has a ground plane thereon for constituting the ground E. Insofar as the reset gate 25 also maintains its zero voltage state, therefore, a single large superconducting loop 23 (indicated by a broken line in the drawing) is formed. As will be understood from the explanation later in this specification, this loop 23 can be thought of as a "binary `1` read loop" or a "current discharge loop."
The operation of the conventional Josephson memory circuit 20 shown in FIG. 4 will now be explained.
The write operation is substantially the same as that explained earlier with respect to FIG. 3. Specifically, for writing binary "1" into the selected superconducting memory loop, control current I.sub.X is applied as the X selection current and binary "1" command current I.sub.M is applied to the control input of the set gate 21 so as to switch over the voltage state of the set gate 21 and cause circuit current I.sub.Y to flow into the circuit current line 12. For writing binary "0", on the other hand, only control current I.sub.X is applied, without applying binary "1" write command current I.sub.M to the set gate 21. In the latter case, while the state of the selected superconducting memory loop prior to the write operation may in some cases be binary "1", this creates no problem since the application of only the control current I.sub.X operates in conjunction with the persisting loop current I.sub.L flowing within the superconducting memory loop 11 to produce an effect which once switches the Josephson switch J.sub.S to the voltage state so as to discharge the persisting loop current I.sub.L. In the conventional Josephson memory circuit 20, however, the current state within the read loop 23 may in some cases become indefinite. This is particularly true following a binary "1" write operation or a binary "1" nondestructive read operation of the type to be explained later and necessitates an operation for reliably discharging from the circuit current line 12 any residual current component that may be present. Thus, prior to the initiation of either the write mode or the read mode, it is necessary to apply a reset current I.sub.RST to the reset gate 25 so as to put loop 23 in the voltage state for a predetermined time period so as to momentarily discharge it.
On the other hand, in the mode for nondestructively reading the information stored in the selected superconducting memory loop 11 (or Josephson memory cell 10), the operation begins with the application of the power source current I.sub.W to the set gate 21 and the power source current I.sub.R to the sense amplifier 22. The power source current I.sub.R can be thought of as a read mode current for informing the external circuitry that the operation is in read mode.
After this state has been established, control current I.sub.X is applied to the control signal line 13 of the selected superconducting memory loop 11. If the binary value stored in the selected superconducting memory loop 11 is "0", since this means that there will be no discharge of persisting loop current I.sub.L to the read loop 23, the sense amplifier 22 will maintain its zero voltage state not withstanding that read mode current I.sub.R is being applied thereto as circuit current. Therefore, since no significant current will pass through the load resistance R.sub.L on the output side of the sense amplifier 22, the external circuitry (not shown) will be able to detect from this fact that the value stored in the selected Josephson memory cell 10 is binary "0".
On the other hand, if the binary value stored in the selected superconducting memory loop 11 or Josephson memory cell 10 is "1", the control current I.sub.X applied to the Josephson switch J.sub.S of the cell 10 concerned will operate in conjunction with the persisting loop current I.sub.L flowing within the superconducting memory loop 11 of the cell to produce an effect causing the Josephson switch J.sub.S of the superconducting memory loop 11 concerned to switch temporarily to the voltage state, whereby discharge current I.sub.LO will pass into the read loop 23 from the superconducting memory loop 11. Then, since the read mode current I.sub.R is applied to the sense amplifier 22 during this read mode operation, the sense amplifier 22 will be switched to the voltage state upon receipt of the discharge current I.sub.LO, whereby the sense amplifier 22 will output sense current I.sub.S representing binary "1" to the load resistance R.sub.L.
If this were all there were to the binary "1" read operation, the read-out would be destructive. As soon as the operations explained so far have been completed, however, the conventional circuit shown in FIG. 4 carries out a rewrite operation so as to produce an effect that is equivalent to nondestructive read-out. Specifically, when the sense amplifier 22 switches to the voltage state and outputs the sense current I.sub.S to the load resistance R.sub.L, the sense current I.sub.S is forwarded through a rewrite signal line 24 to the input of the set gate 21, which is at this time being supplied with the power source current I.sub.W. As a result, the control input of the set gate 21 receives a rewrite command current that is functionally identical to the binary "1" command current mentioned earlier. Thus, by the same mechanism as described above, the set gate 21 switches to the voltage state, causing circuit current I.sub.Y to flow into the circuit current line 12 at this time. Since control current I.sub.X for read-out is still being supplied to the selected Josephson memory cell 10 when this occurs, the combined action of the two currents causes binary "1" to be rewritten to the superconducting memory loop of the Josephson memory cell 10. The result is thus the equivalent of nondestructive read-out.
Earlier methods for achieving nondestructive read-out included highly complicated ones requiring a dedicated sense gate for every memory cell and ones using three operating states based on the number of flux quanta (two, one or zero, for example) captured by the superconducting memory loop and were deficient both in ability to adapt to different operating conditions and in degree of design freedom. While the nondestructive read-out principle embodied by the circuit shown in FIG. 4 and explained in the foregoing is far superior to that of these earlier circuits, it still has room for improvement. For instance, one disadvantage that can be pointed out is the intrinsic need in the case of the arrangement shown in FIG. 4 to dispose a set gate 21 and a sense amplifier 22 separately at opposite ends of the respective circuit current lines 12. The long rewrite signal line 24 required for supplying the rewrite command current I.sub.S from the sense amplifier 22 to the set gate 21 in this arrangement is disadvantageous from the point of slowing the operating speed of the memory circuit but is even a greater problem as a factor increasing structural complexity, reducing packing density and decreasing the degree of freedom of memory cell and memory column layout when the memory circuit is to be integrated on a single chip. While it is not impossible to devise a circuit layout that brings the set gate 21 and the sense amplifier 22 close together on the IC substrate, this can be achieved only at the expense of increasing the length of the control input line extending from the opposite end of the circuit current line 12 through the reset gate 25 to the sense amplifier 22 and, therefore, is not a solution capable of overcoming the various problems discussed above.
Another shortcoming of the conventional Josephson memory circuit 20 shown in FIG. 4 is that the need touched on briefly earlier to eliminate the indefinite current state that can be expected to arise in the superconducting read-out loop 23 after a binary "1" write or nondestructive read operation makes the reset gate 25 a substantially indispensable circuit element. From the point of circuit simplification and the realization of a higher degree of integration, however, it would be preferable to do away with this reset gate provided only to mitigate a negative aspect of the circuit. It would be even more preferable to provide a fundamental solution by altogether eliminating the occurrence of the indefinite current state that makes the gate necessary in the first place. In addition to such circuit and integration density related problems, the conventional Josephson memory circuit 20 has a further drawback in that a special timing arrangement is required solely for the reset gate 25. Specifically, it is necessary to provide a dedicated power source (generally a unipolar pulse source) for supplying the reset current I.sub.RST. As was reported in newspapers throughout Japan on Dec. 13, 1989, the present assignee was the first anywhere in the world to carry out successful test operation of a Josephson computer. This has helped to convince the assignee that Josephson circuits of the type under discussion here can be expected to develop at a rapid ace, and from this it can easily be anticipated that the different types of timing required in such circuits will become extremely numerous. The assignee thus desires to contribute to reducing the number of different types of timing required, even if only by one.
The earlier mentioned Japanese patent public disclosure describing the memory circuit indicated in FIG. 4 states that as the means for eliminating the residual current it is possible, in lieu of providing the reset gate 25, simply to provide a resistor in series within the superconducting read-out loop 23 so that the residual current can be dissipated by conversion to heat. As, however, such a resistor would also constitute a cause for loss of the regular discharge current from the superconducting memory loop 11, the reset gate becomes necessary at the practical application level.